The present invention relates to a synthesizer using a PLL (phase-locked loop) circuit, which is hereinafter called a PLL synthesizer. More specifically, the invention relates to a PLL synthesizer which can provide oscillation frequencies at small step intervals and which responds in a sufficiently short time.
FIG. 1 shows a well known PLL oscillation circuit. This PLL oscillation circuit has a voltage-controlled oscillator (VCO) 41 with an oscillation frequency that can be operated by a control voltage. It also has a frequency divider (DIV) 42 for dividing the frequency of a signal supplied from the voltage-controlled oscillator 41 at a dividing ratio set by an input set value. Finally, the circuit has a phase comparator (PC) 43 to perform a phase comparison between an output signal of the frequency divider 42 and a reference frequency signal. It also supplies the voltage-controlled oscillator 41 with a phase error signal as the control voltage. The phase comparator 43 has a filter which can interrupt pulse-like signal components occurring in every phase comparison.
In this PLL oscillation circuit, an oscillation frequency fo is given by fo=k.times.fr where k is the dividing ratio of the frequency divider 42 and fr is a frequency of the reference frequency signal. Since the dividing ratio k is a positive integer, this PLL oscillation circuit provides oscillation frequencies at a step interval of fr.
Oscillation frequencies with smaller step intervals can be obtained with this PLL oscillation circuit by reducing the reference frequency fr. However, if the reference frequency fr is reduced, the cutoff frequency of the filter of the phase comparator 43 can also be lowered. If the cutoff frequency of the filter of the phase comparator 43 is reduced, the time constant of the filter is increased, which elongates the response time until stabilization of the output. That is, this PLL oscillation circuit has a problem that if it is attempted to obtain oscillation frequencies with smaller step intervals, the response time until stabilization of the output in response to switching of the oscillation frequency becomes longer.
FIG. 2 shows a conventional PLL oscillation circuit that has solved the above problem. This PLL oscillation circuit has the following components. Reference numeral 51 denotes a voltage-controlled oscillator (VCO). A first frequency divider (DIV1) 52 divides an oscillation frequency fo of an output signal of the voltage-controlled oscillator 51 at a ratio of k (positive integer). A second frequency divider (DIV2) 53 further divides the frequency of an output signal of the first frequency divider 52. A phase comparator (PC) 54 compares the phase of the output signal of the first divider 52 with that of a reference frequency signal. A triangular wave oscillator (TRI OSC) 55 generates a triangular wave based on a frequency-divided signal as output from the second frequency divider 53. An adder (SUM) 56 adds the output signals of the phase comparator 54 and the triangular oscillator 55.
In this PLL oscillation circuit, the frequency of the signal input to the first frequency divider 52 is usually divided at a ratio of k or k+j (j is an integer other than 0). The frequency-divided signal is input to the phase comparator 54, where it is subjected to phase comparison with the reference frequency (fr) signal. On the other hand, the frequency-divided signal output from the first frequency divider 52 is input to the second frequency divider 53, where it is subjected to frequency division at a ratio s. The frequency-divided signal as output from the second frequency divider 53 is input to the triangular wave oscillator 55. Further, the second frequency divider 53 supplies a switching signal to the first frequency divider 52 at a predetermined timing to effect switching between the frequency division of k and that of k+j.
The triangular wave oscillator 55 generates a triangular wave with a period T based on the frequency-divided signal supplied from the second frequency divider 53. The output signal from the phase comparator 54 and the triangular wave from the triangular wave oscillator 55 are subjected to addition (or subtraction) in the adder 56. As a result, a varying signal, having the period T, is removed from the output signal of the phase comparator 54. An output signal from the adder 56 is supplied, as a frequency control signal, to the voltage-controlled oscillator 51.
In the case with frequency division of k+j where j=1 and the first frequency divider 52 performs m times of frequency division of k+1 and s-m times of frequency division of k. Then, the output frequency fo is expressed as ##EQU1## It is understood that oscillation frequencies can be obtained with the step interval fr/s. That is, it is possible to obtain oscillation frequencies with small step intervals without reducing the frequency fr of the reference frequency signal. This type of PLL oscillation circuit is, for example, disclosed in Japanese Unexamined Patent Publication No. Sho. 63-28131 (1988).
However, the above method for decreasing the step intervals of oscillation frequencies by using a triangular wave has the following problem. Since the frequency division number of the period T depends on the oscillation frequency, an error in the oscillation frequency of the triangular wave directly deteriorates the stability of the oscillation frequency of the voltage-controlled oscillator 51.